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merged 1 commit into from
Jul 23, 2025
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AMDGPU/GlobalISel: Add regbanklegalize rules for uniform global loads #145909

merged 1 commit into from
Jul 23, 2025

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This was referenced Jun 26, 2025
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@petar-avramovic petar-avramovic marked this pull request as ready for review June 26, 2025 14:55
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llvmbot commented Jun 26, 2025 •
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@llvm/pr-subscribers-llvm-globalisel

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Author: Petar Avramovic (petar-avramovic)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/145909.diff

2 Files Affected:

  • (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp (+3)
  • (added) llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll (+95)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index a60855cc4f2d6..41d24c8797426 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -671,6 +671,9 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
       .Any({{{UniB256, UniP1}, isAlign4 && isUL}, {{SgprB256}, {SgprP1}}})
       .Any({{{UniB512, UniP1}, isAlign4 && isUL}, {{SgprB512}, {SgprP1}}})
       .Any({{{UniB32, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB32}, {SgprP1}}})
+      .Any({{{UniB64, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB64}, {SgprP1}}})
+      .Any({{{UniB96, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB96}, {SgprP1}}})
+      .Any({{{UniB128, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB128}, {SgprP1}}})
       .Any({{{UniB256, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB256}, {VgprP1}, SplitLoad}})
       .Any({{{UniB512, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB512}, {VgprP1}, SplitLoad}})
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll
new file mode 100644
index 0000000000000..d7dbde3a2bb00
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll
@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s
+
+define amdgpu_ps void @uniform_load_32(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1, ptr addrspace(1) inreg %ptr2) {
+; CHECK-LABEL: uniform_load_32:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    v_mov_b32_e32 v0, 0
+; CHECK-NEXT:    global_load_dword v1, v0, s[0:1] glc dlc
+; CHECK-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-NEXT:    global_load_dword v2, v0, s[2:3] glc dlc
+; CHECK-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-NEXT:    v_readfirstlane_b32 s0, v1
+; CHECK-NEXT:    v_readfirstlane_b32 s1, v2
+; CHECK-NEXT:    s_add_i32 s0, s0, s1
+; CHECK-NEXT:    v_mov_b32_e32 v1, s0
+; CHECK-NEXT:    global_store_dword v0, v1, s[4:5]
+; CHECK-NEXT:    s_endpgm
+  %load0 = load volatile i32, ptr addrspace(1) %ptr0
+  %load1 = load volatile i32, ptr addrspace(1) %ptr1
+  %sum = add i32 %load0, %load1
+  store i32 %sum, ptr addrspace(1) %ptr2
+  ret void
+}
+
+define amdgpu_ps void @uniform_load_64(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
+; CHECK-LABEL: uniform_load_64:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    v_mov_b32_e32 v2, 0
+; CHECK-NEXT:    global_load_dwordx2 v[0:1], v2, s[0:1] glc dlc
+; CHECK-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-NEXT:    v_readfirstlane_b32 s0, v0
+; CHECK-NEXT:    v_readfirstlane_b32 s1, v1
+; CHECK-NEXT:    s_add_i32 s0, s0, s1
+; CHECK-NEXT:    v_mov_b32_e32 v0, s0
+; CHECK-NEXT:    global_store_dword v2, v0, s[2:3]
+; CHECK-NEXT:    s_endpgm
+  %load = load volatile <2 x i32>, ptr addrspace(1) %ptr0
+  %elt0 = extractelement <2 x i32> %load, i32 0
+  %elt1 = extractelement <2 x i32> %load, i32 1
+  %sum = add i32 %elt0, %elt1
+  store i32 %sum, ptr addrspace(1) %ptr1
+  ret void
+}
+
+define amdgpu_ps void @uniform_load_96(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
+; CHECK-LABEL: uniform_load_96:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    v_mov_b32_e32 v3, 0
+; CHECK-NEXT:    global_load_dwordx3 v[0:2], v3, s[0:1] glc dlc
+; CHECK-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-NEXT:    v_readfirstlane_b32 s0, v0
+; CHECK-NEXT:    v_readfirstlane_b32 s1, v1
+; CHECK-NEXT:    v_readfirstlane_b32 s4, v2
+; CHECK-NEXT:    s_add_i32 s0, s0, s1
+; CHECK-NEXT:    s_add_i32 s0, s0, s4
+; CHECK-NEXT:    v_mov_b32_e32 v0, s0
+; CHECK-NEXT:    global_store_dword v3, v0, s[2:3]
+; CHECK-NEXT:    s_endpgm
+  %load = load volatile <3 x i32>, ptr addrspace(1) %ptr0
+  %elt0 = extractelement <3 x i32> %load, i32 0
+  %elt1 = extractelement <3 x i32> %load, i32 1
+  %elt2 = extractelement <3 x i32> %load, i32 2
+  %sum0 = add i32 %elt0, %elt1
+  %sum = add i32 %sum0, %elt2
+  store i32 %sum, ptr addrspace(1) %ptr1
+  ret void
+}
+
+define amdgpu_ps void @uniform_load_128(ptr addrspace(1) inreg %ptr0, ptr addrspace(1) inreg %ptr1) {
+; CHECK-LABEL: uniform_load_128:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    global_load_dwordx4 v[0:3], v4, s[0:1] glc dlc
+; CHECK-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-NEXT:    v_readfirstlane_b32 s0, v0
+; CHECK-NEXT:    v_readfirstlane_b32 s1, v1
+; CHECK-NEXT:    v_readfirstlane_b32 s4, v2
+; CHECK-NEXT:    v_readfirstlane_b32 s5, v3
+; CHECK-NEXT:    s_add_i32 s0, s0, s1
+; CHECK-NEXT:    s_add_i32 s0, s0, s4
+; CHECK-NEXT:    s_add_i32 s0, s0, s5
+; CHECK-NEXT:    v_mov_b32_e32 v0, s0
+; CHECK-NEXT:    global_store_dword v4, v0, s[2:3]
+; CHECK-NEXT:    s_endpgm
+  %load = load volatile <4 x i32>, ptr addrspace(1) %ptr0
+  %elt0 = extractelement <4 x i32> %load, i32 0
+  %elt1 = extractelement <4 x i32> %load, i32 1
+  %elt2 = extractelement <4 x i32> %load, i32 2
+  %elt3 = extractelement <4 x i32> %load, i32 3
+  %sum0 = add i32 %elt0, %elt1
+  %sum1 = add i32 %sum0, %elt2
+  %sum = add i32 %sum1, %elt3
+  store i32 %sum, ptr addrspace(1) %ptr1
+  ret void
+}

arsenm
arsenm reviewed Jun 27, 2025
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lgtm with test nits

llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll Outdated
@@ -0,0 +1,95 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s
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Suggested change
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck %s

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why remove verify-machineinstrs?

llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll Outdated
@@ -0,0 +1,95 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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Test name could be more specific, it's uniform VGPR loads.

llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll Outdated
store i32 %sum, ptr addrspace(1) %ptr2
ret void
}

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Is it worth testing other cases with other element types? ptr, i16 vectors, fp, etc.

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Check is for size in bits not specific type.
Maybe later when we go over all possible load types? I wanted to get readanylane combines out of the way first.

arsenm
arsenm reviewed Jun 27, 2025
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llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll Outdated
%sum = add i32 %sum1, %elt3
store i32 %sum, ptr addrspace(1) %ptr1
ret void
}
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Alignment check not stressed?

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Not sure about this one. Align condition is from old regbankselect but maybe we don't need it, or it is wrong?
Legalizer deals with many cases of Align and splits load.
Do you know what we need to check for considering align?

@petar-avramovic petar-avramovic force-pushed the users/petar-avramovic/rbl-uniform-loads branch from 3a23ac4 to c6461ff Compare June 27, 2025 10:39
@petar-avramovic petar-avramovic force-pushed the users/petar-avramovic/rbl-uniform-loads branch from c6461ff to dea46d7 Compare June 27, 2025 13:52
petar-avramovic
petar-avramovic commented Jun 27, 2025
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llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
; CHECK-NEXT: global_store_dword v0, v1, s[4:5]
; CHECK-NEXT: s_endpgm
%load0 = load volatile i32, ptr addrspace(1) %ptr0
%load1 = load i32, ptr addrspace(1) %ptr1, align 1
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updated with cases that hit align check

@petar-avramovic petar-avramovic force-pushed the users/petar-avramovic/rbl-uniform-loads branch from dea46d7 to cd3da9d Compare July 23, 2025 14:29
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petar-avramovic commented Jul 23, 2025 •
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Merge activity

  • Jul 23, 2:30 PM UTC: A user started a stack merge that includes this pull request via Graphite.
  • Jul 23, 2:33 PM UTC: Graphite rebased this pull request as part of a merge.
  • Jul 23, 2:35 PM UTC: @petar-avramovic merged this pull request with Graphite.

@petar-avramovic petar-avramovic force-pushed the users/petar-avramovic/rbl-uniform-loads branch from cd3da9d to e8d6fd7 Compare July 23, 2025 14:32
@petar-avramovic petar-avramovic merged commit dfd3935 into main Jul 23, 2025
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@petar-avramovic petar-avramovic deleted the users/petar-avramovic/rbl-uniform-loads branch July 23, 2025 14:35
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llvm-ci commented Jul 23, 2025

LLVM Buildbot has detected a new failure on builder lldb-aarch64-windows running on linaro-armv8-windows-msvc-05 while building llvm at step 6 "test".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/141/builds/10371

Here is the relevant piece of the build log for the reference 
Step 6 (test) failure: build (failure)
...
PASS: lldb-unit :: ValueObject/./LLDBValueObjectTests.exe/2/12 (2272 of 2281)
PASS: lldb-unit :: ValueObject/./LLDBValueObjectTests.exe/3/12 (2273 of 2281)
PASS: lldb-unit :: ValueObject/./LLDBValueObjectTests.exe/4/12 (2274 of 2281)
PASS: lldb-unit :: ValueObject/./LLDBValueObjectTests.exe/5/12 (2275 of 2281)
PASS: lldb-unit :: ValueObject/./LLDBValueObjectTests.exe/6/12 (2276 of 2281)
PASS: lldb-unit :: ValueObject/./LLDBValueObjectTests.exe/7/12 (2277 of 2281)
PASS: lldb-unit :: ValueObject/./LLDBValueObjectTests.exe/8/12 (2278 of 2281)
PASS: lldb-unit :: ValueObject/./LLDBValueObjectTests.exe/9/12 (2279 of 2281)
PASS: lldb-unit :: tools/lldb-server/tests/./LLDBServerTests.exe/0/1 (2280 of 2281)
TIMEOUT: lldb-unit :: Host/./HostTests.exe/6/12 (2281 of 2281)
******************** TEST 'lldb-unit :: Host/./HostTests.exe/6/12' FAILED ********************
Script(shard):
--
GTEST_OUTPUT=json:C:\Users\tcwg\llvm-worker\lldb-aarch64-windows\build\tools\lldb\unittests\Host\.\HostTests.exe-lldb-unit-9884-6-12.json GTEST_SHUFFLE=0 GTEST_TOTAL_SHARDS=12 GTEST_SHARD_INDEX=6 C:\Users\tcwg\llvm-worker\lldb-aarch64-windows\build\tools\lldb\unittests\Host\.\HostTests.exe
--

Note: This is test shard 7 of 12.

[==========] Running 8 tests from 6 test suites.

[----------] Global test environment set-up.

[----------] 1 test from FileSystemTest

[ RUN      ] FileSystemTest.FileAndDirectoryComponents

[       OK ] FileSystemTest.FileAndDirectoryComponents (0 ms)

[----------] 1 test from FileSystemTest (0 ms total)



[----------] 1 test from HostInfoTest

[ RUN      ] HostInfoTest.GetAugmentedArchSpec

[       OK ] HostInfoTest.GetAugmentedArchSpec (1 ms)

[----------] 1 test from HostInfoTest (1 ms total)



[----------] 2 tests from MainLoopTest

[ RUN      ] MainLoopTest.ReadPipeObject


--
exit: 15

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@nhaehnle nhaehnle nhaehnle approved these changes

@Pierre-vh Pierre-vh Pierre-vh approved these changes

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